1. Field of the Invention
The invention relates to molecular beam epitaxial growth methods of semiconductor device fabrication, and in particular a method of forming a semiconductor device having a simiconductor-metal-semiconductor structure in which the metal is porous and the two layers of semiconductor material are epitaxially matched, and devices made thereby.
2. Description of the Prior Art
The use of porous or perforated layers in a semiconductor structure is known for certain special purpose applications, such as in gas detectors, solar cells, and lasers. U.S. Pat. No. 4,505,803 describes an oxygen concentration detector which employs a porous diffusion layer of alumina spinel on the surface of a semiconductor body. U.S. Pat. No. 4,449,286 describes a solar cell including a silicon layer which is porous. U.S. Pat. No. 4,264,381 describes the fabrication of injection lasers in which a porous host diffusion layer is employed.
More particularly, the use of a porous metal layer in a semiconductor-metal-semiconductor structure has been suggested in "The Metal Gate Transistor," J. Lindmayer, Proceedings of the IEEE, 1964, p. 1751 and more recently in "Transistor Action in Si/CoSi.sub.2 /Si Heterostructures", J. Hensel, A. Levi, R. Tung and J. Gibson, Applied Physics Letters, Vol. 47, p. 151, July 15, 1985, in which electrical conduction from one semiconductor region to another is proposed to be modulated by electric fields existing in holes in the metal layer. In the structures disclosed in such references, spontaneously-occurring perforations in the metal are used as the basis for electrical modulation of the current passing from one semiconductor layer to another, typically in an epitaxial structure consisting of silicon, cobalt silicide and silicon. The growth of the upper layer of epitaxial silicon in such structures is achieved by the use of epitaxial cobalt silicide (CoSi.sub.2) or other epitaxial silicide which is lattice matched to silicon to within a few percent. Further, regular lattices or networks of holes in metal layers formed by lithographic means are used both as conducting paths between two semiconductor layers and as a means of allowing epitaxial growth in the fabrication of devices known as permeable base transistors, such as discussed in "Fabrication and Microwave Performance of the Permeable Base Transistor," C. O. Bozler, G. D. Alley, R. A. Murphy, D. C. Flanders and W. T. Lindly, IEEE Tech. Dig. Int. Electron Devices Meeting 384 (1979).
The silicon/metal silicide heterostructures grown by molecular beam epitaxy known in the prior art utilize a technique known as strained layer epitaxy which requires that the intermediate layer such as the metal silicide be substantially latticed matched with the native or lower layer. The strain induced in the material itself provides lattice matching, however such lattice matching is not without disadvantages. The strain created in the intermediate layer may be transferred to the semiconductor, which may result in defects in the semiconductor layer which may affect active devices therein. The lattice matching between the upper semiconductor layer and the lower semiconductor layer is achieved by virtue of the upper layer being lattice matched with the intermediate layer which in turn is lattice matched with the lower layer. The lattice matching therefore does not take place by growth in a direction parallel to the plane of the semiconductor body (which is known as lateral epitaxy) and the reproducibility of the prior art epitaxial growth technique in a production environment for a large number of wafers may be questionable.
More importantly, the silicon/metal silicide heterostructures of the prior art are limited to specific classes of semiconductors and compounds. There are no known intermediate metal layers for use with semiconductors of the III-V classes which would provide similar structures of silicon/metal silicide heterostructures, and even with silicon semiconductor devices the use of materials such as refractory metals which are substantially mismatched to the structure of the silicon is not possible. Thus, if the physical or electrical characteristics of the intermediate layer required the use of a particular type of metal which was not lattice matched with the lower layer, the teachings of the prior art heterostructures would be of no use.
With respect to the permeable base transistor structure described above in the Bozler et al. reference, it is noted that the metal is patterned after deposition by a separate lithographic step to produce a structure containing openings in a regular pattern. The metal layer is not porous when deposited, and the requirement for separate patterning and etching steps to produce holes in the metal layer is also not desirable from a production viewpoint.
"Silicon/metal Silicide Heterostructures Grown by Molecular Beam Epitaxy", by J. C. Bean and J. M. Poate, Applied Physics Letters, Vol. 37, p. 643, Oct. 1, 1980, discloses a method for the overgrowth of epitaxial silicide metal layers on silicon and subsequent overgrowth of epitaxial silicon layers on the silicide by molecular beam epitaxy (MBE) using lattice matching of the silicide to silicon to establish a template for the upper silicon layer. Such technique of silicide matching is also disclosed in U.S. Pat. No. 3,375,418 to R. R. Garnache and F. L. Vogel, in which restricted area geometries are used to enhance monocrystallinity of the silicide layer for silicides which normally do not match silicon very well. An application of such technique to the production of a device is discussed in E. Rosencher, S. Delage, T. Campidelli, and F. Armand D'Avitaya, "Transistor Effect in Monolithic Si/CoSi.sub.2 /Si Epitaxial Structures", Electronics Letters, Vol. 20, p. 762, Sept. 13, 1984.
The semiconductor-metal semiconductor structures described in the references summarized above are disadvantageous in that they require either the use of a metal layer which is closely epitaxially matched to the semiconductor layers, as in the work of Bean et al. and Garnache et al. described above, or they require a separate processing step of patterning as in the work of Bozler et al. to achieve epitaxial growth of semiconductor layers deposited after deposition of a non-epitaxial metal layer. Prior to the present invention, the epitaxial growth of a second semiconductor layer has not been achieved as part of an uninterrupted growth sequence in which control of temperature, deposition rate and metal thickness are used to produce metallic layers of a porous nature suitable for the growth of a second semiconductor layer epitaxially matched to the first. Prior to the present invention the free use of non-epitaxial metallic layers to create a semiconductor-metal-semiconductor structure in an uninterrupted growth sequence has not been suggested.